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? 200 7 semiconductor components industries, llc. publication order number: december - 2017, rev . 2 fan3100t/d fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver fan3100 c / fan3100t single 2 a high - speed, low - side gate driver features ? 3 a peak sink/source at v dd = 12 v ? 4.5 to 18 v operating range ? 2.5 a sink / 1.8 a source at v out = 6 v ? dual - logic inputs allow configuration as non - inverting or inverting w ith enab le function ? i nternal r esistors t urn d river o ff if n o inputs ? 13 ns typical rise time and 9 ns typical fall - time w ith 1 n f load ? choice of ttl or cmos i nput t hresholds ? millerdrive? technology ? typical propagation delay time u nder 2 0 ns w ith input falling or r ising ? 6 - lead, 2x2 mm ml p o r 5 - pin , sot23 packages ? rated f r om ? 40c to 1 25c ambient applications ? sw itch ed- mode pow er supplies (smps) ? high - ef f iciency mosfet sw itching ? synchronous rectifier circuits ? dc- to - dc converters ? motor control descript ion the fan3100 2 a g ate d river is designed to drive an n - channel enhancement - mode mosfet in low - side sw itching applications by providing high peak current pulses during the short sw itching intervals. the driver is available w ith either ttl (fan3100 t ) or cmos (fan310 0c ) input thresholds. internal circuitry provides an under - voltage lockout function by holding the output low until the supply voltage is w ithin the operating range . t he fan3100 delivers fast mosfet sw i tching performance , w hich helps maximize efficiency in hig h - frequency pow er converter designs. fan3100 drivers incorporate millerdrive? architecture for the final output stage. this bipolar - mosfet combination provides high peak current during the miller plateau stage of the mosfet turn - on / turn - off process to mi nimize sw itching loss, w hile providing rail - to - rail voltage sw ing and reverse current capability. the fan3100 also offers dual inputs that can be configured to operate in non - inverting or inverting mode and allow implementation of an ena ble function. i f on e or both inputs are left unconnected, internal resistors bias the inputs such that the output is pulled low to hold the pow er mosfet off . the fan3100 is available in a lead - free finish , 2x2 mm, 6 - l ead, molded leadless package ( mlp ) for the smallest size w ith excellent thermal performance ; or industry - standard , 5 - pin , sot23. functional pin configuration s 1 6 5 2 4 3 in+ agnd vdd in- pgnd out 1 2 3 5 4 vdd gnd in+ in? out
www.onsemi.com 2 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver figure 1. 6 - lead mlp (top view ) figure 2. sot23 - 5 (top view ) order ing information part number input threshold package packing method quantity / reel fa n3 100 cmpx c mos 6 - lead, 2x2 mm mlp tape & reel 3000 fa n3 100c s x cmos 5 - pin , so t23 tape & reel 3000 fa n3 100 tmpx ttl 6 - lead, 2x2 mm mlp tape & reel 3000 fa n3 100t s x ttl 5 - pin , so t23 tape & reel 3000 package outlines 1 6 5 2 4 3 in+ agnd vdd in? pgnd out 1 2 3 5 4 vdd gnd in+ in? out figure 3. 6 - lead mlp ( top view ) figure 4. sot23 - 5 (top view ) the rmal characteristics ( 1 ) package 6 - lead, 2x2 mm molded leadless package (mlp) 2.7 133 58 2.8 42 c/w sot23 - 5 56 99 157 51 5 c/w notes: 1. estimates derived from thermal simulation; actual values depend on the applicat ion. 2. theta_jl ( jl ): thermal resistance betw een the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a pcb. 3. theta_jt ( jt ): thermal resistance betw een the semiconductor junction and t he top surface of the package, assuming it is held at a uniform temperature by a top - side heatsink. 4. theta_ja ( ja ): thermal resistance betw een junction and ambient, dependent on the pcb design, heat sinking, and airflow . the value given is for natural convection w ith no heatsink using a 2sp2 board , as specified in jedec standards jesd5 1 - 2, jesd51 - 5, and jesd51 - 7, as appropriate . 5. ps i_ jb ( jb ): thermal characterization parameter providing correlation betw een semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in note 4 . for the mlp - 6 package, the board reference is defined as the pcb copper connected to the thermal pad and protruding from either end of the package. for the sot23 - 5 package, the board reference is defined as the pcb copper adjacent to pin 2 . 6. ps i_ jt ( jt ): thermal characterization parameter providing correlation betw een the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in note 4 .
www.onsemi.com 3 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver pin definitions sot23 pin # mlp pin # name pin description 1 3 v dd supply voltage . provides pow er to the ic. 2 a gnd analog ground for input signals (mlp only). c onnect to pgnd under neath the ic. 2 gnd ground (sot - 23 only). c ommon ground referen ce for inp ut and output circuits . 3 1 in+ no n - inverting input . connect to v dd to enable output . 4 6 in - inverting input . connect to a gnd or p gnd to enable output . 5 4 out gate drive output : held low unless required inputs are present and v dd is above uvlo thresh old. pa d p1 therm al pad (mlp only). exposed metal on the bottom of the package , w hich is electrically connected to pin 5 . 5 pgnd pow er ground (mlp only). for output drive circuit; separates sw itching noise from inputs. output logi c in+ in ? out 0 ( 7 ) 0 0 0 ( 7 ) 1 ( 7 ) 0 1 0 1 1 1 ( 7 ) 0 no t e : 7. default i nput signal if no external connection is made .
www.onsemi.com 4 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver block diagram s in - 4 1 vdd 5 out 2 gnd uvlo v dd_ok in+ 3 100k? 100k? 100k? figure 5. sim plified block diagram ( sot23 pin - out) in - 6 3 vdd 4 out 5 pgnd uvlo v dd_ok in+ 1 100k? 100k? 100k? agnd 2 0.4? figure 6. sim plified block diagram (mlp pin - out)
www.onsemi.com 5 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute max imum r at ings are stress ratings only. symbol parameter min. max. unit v dd v dd to p gnd - 0.3 20.0 v v in voltage o n in+ and in - to gnd , a gnd, or pgnd gnd - 0.3 v dd + 0.3 v v out voltage o n out to gnd, a gnd, or pgnd gnd - 0.3 v dd + 0.3 v t l lead soldering temperat ure (10 s econds) + 260 oc t j junction temperature - 55 + 150 oc t stg storage temperature - 65 + 150 oc recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating con ditions are specified to ensure optimal performance to the datasheet specifications. on semiconductor does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v dd supply voltage range 4.5 18.0 v v in inp ut voltage in+, in - 0 v dd v t a operating ambient temperature - 40 + 125 oc
www.onsemi.com 6 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver electrical characteristics unless otherw ise noted, v dd = 12 v , t j = - 40c to + 12 5c. currents are defined as positive into the device and negative out of the device. symbol parame ter conditions min. typ. max. unit s upply v dd o perating r ange 4.5 18.0 v i dd supply current inputs/en n ot c onnected fan3100 c ( 8 ) 0. 20 0. 35 ma fan3100t 0.5 0 0.8 0 ma v on turn - o n v oltage 3.5 3.9 4.3 v v off turn - off v o ltage 3.3 3.7 4.1 v i nputs (fan3100t) v inl _t in+, in - logic low voltage, m ax imum 0.8 v v inh _t in+, in - logic high voltage, m in imum 2.0 v i in+ non - inverting i nput in from 0 to v dd - 1 175 a i in - inverting i nput in from 0 to v dd - 175 1 a v hys in+, in - logic hysteresis voltage 0.2 0.4 0.8 v inputs (fan3100c) v inl_c in+, in - logic low voltage 30 %v dd v inh_c in+, in - logic high voltage 70 %v dd i inl in current, low in from 0 to v dd - 1 175 a i inh in current, high in from 0 to v dd - 175 1 a v hys_c in+, in - logic hysteresis voltage 17 %v dd output i sink out c urrent, m id - v oltage, s inking ( 9 ) out at v dd /2, c loa d = 0.1 f, f = 1 khz 2.5 a i source out c urrent, m id - v oltage, s ourcing ( 9 ) out at v dd /2, c loa d = 0.1 f, f = 1 khz - 1.8 a i pk_sink out c urrent, p eak, s inking ( 9 ) c loa d = 0.1 f, f = 1 khz 3 a i pk_source out c urrent, p eak, s ourcing ( 9 ) c loa d = 0.1 f, f = 1 k hz - 3 a t rise output rise time ( 10) c loa d = 1000 pf 13 20 ns t fall output fall time ( 10) c loa d = 1000 pf 9 14 ns t d1 , t d2 output prop. delay, cmos inputs ( 10) 0 ? 12 v in ; 1 v/ns slew rate 7 15 28 ns t d1 , t d2 output prop. delay, ttl inputs ( 10) 0 ? 5 v in ; 1 v/ns slew rate 9 16 30 ns i rvs output reverse current withstand ( 9 ) 500 ma no t e s : 8. low er supply current due to inactive ttl circuitry. 9. not tested in production. 10. see timing diagrams of figure 7 and figure 8 .
www.onsemi.com 7 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver timing diagrams 90% 10% output input t d1 t d2 t rise t fall v inl v inh 90% 10% output input t d1 t d2 t fall t rise v inl v inh figure 7. no n - inverting figure 8. i nverting
www.onsemi.com 8 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver typical performance characteristics typical characteristics are provided at 25c and v dd =12 v unless otherw ise noted. figure 9. i dd (static) vs. supply voltage figure 10. i dd (static) vs. supply voltage figure 11. i dd ( no - load) vs. frequency figure 12. i dd ( no - load) vs. frequency figure 13. i dd (1 nf load) vs. frequency figure 14. i dd (1 nf load) vs. frequency
www.onsemi.com 9 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver typical performance characteristics typical characteristics are provided at 25c and v dd =12 v unless otherw ise noted. figure 15. i dd (static) vs. temperature figure 16. i dd (static) vs. temperature figure 17. input thresholds vs. supply voltage figure 18. input thresholds vs. supply voltage figure 19. input thresholds % vs. supply voltage
www.onsemi.com 10 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver typical performance characteristics typical characteristics are provided at 25c and v dd =12 v unless otherw ise noted. figure 20. cmos input thresholds vs. temperature figure 21. ttl input thresholds vs. temperature figure 22. uvlo thresholds vs. temperature figure 23. uvlo hysteresis vs. temperature figure 24. propagation delay vs. supply voltage figure 25. propagation delay vs. supply voltage
www.onsemi.com 11 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver typical performance characteristics typical characteristics are provided at 25c and v dd =12 v unless otherw ise noted. figure 26. propagation delay vs. supply voltage figure 27. propagation delay vs. supply voltage figure 28. propagation delay vs. temperature figure 29. propagation delay vs. temperature figure 30. propagation delay vs. temperature figure 31. propagation delay vs. temperature
www.onsemi.com 12 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver typical performance characteristics typical characteristics are provided at 25c and v dd =12 v unless otherw ise noted. figure 32. fall tim e vs. supply voltage figure 33. rise time vs. supply voltage figure 34. rise and fall time vs. temperature figure 35. rise / fall waveform s w ith 1 nf load figure 36. rise / fall waveform s w ith 10 nf load
www.onsemi.com 13 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver typical performance characteristics typical characteristics are provided at 25c and v dd =12 v unless otherw ise noted. figure 37. quas i - static sourc e current w ith v dd =12 v figure 38. quas i - static sink current w ith v dd =12 v figure 39. quas i - static source current w ith v dd =8 v figure 40. quas i - static sink current w ith v dd =8 v 470 f al . el . v dd v out 1 f ceramic 4 . 7 f ceramic c load 0 . 1 f i out in 1 khz current probe lecroy ap 015 figure 41. quas i - static i out / v out test circuit
www.onsemi.com 14 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver applications information input thresholds the fa n3 100 offers ttl or cmos input thresholds . in the fa n3 100t , the input thresholds meet industry - standard ttl logic thresholds , independent of the v dd voltage , and there is a hysteresis voltage of approximately 0.4 v . these levels permit the inputs to be driven from a range of input logic signal levels for w hich a voltage over 2 v is considered logic high . t he driving signal for the ttl inputs should have fast rising and falling edges w ith a slew rate of 6 v/s or faster, so the rise time fro m 0 to 3.3 v should be 550 ns or less . with reduced slew rate , circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input, causing erratic operation. in the fan3 100c , the logic input thresholds are d ependent on the v dd level and, w ith v dd of 12 v , the logic rising edge threshold is approximately 5 5 % of v dd and th e input falling edge threshold is approximately 38 % of v dd . the cmos input configuration offers a hysteresis voltage of approximately 17 % of v dd . the cmos inputs can be used w ith relatively slow edges (approaching dc) if good decoupling and bypass techniques are incorporated in the system design to prevent noise from violating the input voltage hysteresis w indow . this allow s set ting precise tim ing intervals by fitting an r - c circuit betw een the controlling signal and the in pin of the driver. the slow rising edge at the in pin of the driver introduces a delay betw een the controlling signal and the out pin of the driver. static supply current in the i dd (static) typical performance graphs ( figure 9 - figure 10 and figure 15 - figure 16 ), the curve is produced w ith all inputs floating (out is low ) and indicates the low est static i dd current for the tested configuration. for other states, additional current flow s through the 100 k ? resistors on the inputs and outputs show n in the block diagram s (see figure 5 - figure 6 ). in these cases, the actual static i dd current is the value obtained from the curves plus this additional current. millerdrive? gate drive technology fa n3 100 drivers incorporate the millerdrive? architecture show n in figure 42 for the output stage, a combination of bipolar and mos devices capable of providing large currents over a w ide range of supply voltage and temperature variations. the bipolar devices carry the bulk of the current as out sw ings betw een 1/3 to 2/3 v dd and the mos devices pull the output to the high or low rail. the purpose of the millerdrive? architecture is to speed up sw itching by providing the highest current during the miller p lateau region w hen the gate - drain capacitance of the mosfet is being charged or discharged as part of the turn - on / turn - off process. for applications t hat have zero voltage sw itching during the mosfet turn - on or turn - off interval, the driver supplies high peak current for fast sw itching even though the miller p lateau is not present. this situation often occurs in synchronous rectifier applications becaus e the body diode is generally conducting before the mosfet is sw itched on. the output pin slew rate is determined by v dd voltage a nd the load on the output. it is not user adjustable, but if a slow er rise or fall time at the mosfet gate is needed, a serie s resistor can be added. input stage v dd v out figure 42. millerdrive? output architecture under - voltage lockout the fa n3 100 start - up logic is optimized to drive ground referenced n - channel mosfets w ith a u nder - v oltage l ock o ut ( uv lo ) function to ensure that t he ic starts up in an orderly fashion. when v dd is rising, yet below the 3.9 v operational level, this circuit holds the output low , regardless of the status of the input pins. after the part is active, the supply voltage must drop 0. 2 v before the part sh uts dow n. this hysteresis helps prevent chatter w hen low v dd supply voltages have noise from the pow er sw itching. this configuration is not suitable for driving high - side p - channel mosfets because the low output voltage of the driver w ould turn the p - chann el mosfet on w ith v dd below 3.9 v . v dd bypass capacitor guidelines to enable this ic to turn a pow er device on quickly, a local , high - frequency , bypass capacitor c byp w ith low esr and esl should be connected betw een the vdd and gnd pins w ith minimal trace length. this capacitor is in addition to bulk electrolytic capacitance of 10 f to 47 f often found on driver and controller bias circuits. a typical criterion for choosing the value of c byp is to keep the ripple voltage on the v dd supply 5%. often this is achieved w ith a value 20 times the equivalent load capacitance c e qv , defined here as q gate /v dd . ceramic capacitors of 0.1 f to 1 f or larger are common choices, as are dielectrics , such as x5r and x7r , w hich have good temperatu re characteristics and high pulse current capability. if circuit noise affect s normal operation, the value of c byp may be increased to 50 - 100 times the c e qv , or c byp may be split into tw o capacitors. one should be a larger value , based on equivalent load c apacitance, and the other a smaller value , such as 1 - 10 nf, mounted closest to the vdd and gnd pins to carry the higher - frequency components of the current pulses.
www.onsemi.com 15 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver layout and connection guidelines the fan3100 incorporates fast - reacting input circuits, sh ort propagation delays, and pow erful output stages capable of delivering current peaks over 2 a to facilitate voltage transition times from under 10 ns to over 100 ns. the follow ing layout and connection guidelines are strongly recommended: ? keep high - curre nt output and pow er ground paths separate from logic input signals and signal ground paths. this is especially critical w hen dealing w ith ttl - level logic thresholds. ? keep the driver as close to the load as possible to minimize the length of high - current t races. this reduces the series inductance to improve high - speed sw itching , w hile reducing the loop area that can radiate emi to the driver inputs and other surrounding circuitry. ? the fan3100 is available in tw o packages w ith slightly different pinouts, off er ing similar performance. in the 6 - pin mlp package, pin 2 is internally connected to the input analog ground and should be connected to pow er ground, pin 5, through a short direct path underneath the ic. in the 5 - pin sot23, the internal analog and pow er g round connections are made through separate, individual bond w ires to pin 2, w hich should be used as the common ground point for pow er and control signals. ? many high - speed pow er circuits can be susceptible to noise injected from their ow n output or other external sources, possibly causing output re - triggering. these effects can be especially obvious if the circuit is tested in breadboard or non - optimal circuit layouts w ith long input, enable, or output leads. for best results, make connections to all pins as short and direct as possible. ? the turn - on and turn - off current paths should be minimized as discussed in the follow ing sections. figure 43 show s the pulsed gate drive current path w hen the gate driver is supplying gate cha rge to turn the mosfet on. the current is supplied from the local bypass capacitor , c byp , and flow s through the driver to the mosfet gate and to ground. t o reach the high peak currents possible, the resistance and inductance in the path should be minimized . the localized c byp acts to contain the high peak current pulses w ithin this driver - mosfet circuit, preventing them from disturbing the sensitive analog circuitry in the pwm controller. pwm v ds v dd c byp fan3100 figure 43. current p ath for mosfet t urn - o n figure 44 show s the current path w hen the gate driver turns the mosfet off . ideally, the driver shunts the current directly to the source of the mosfet in a small circuit loop. for fast turn - off times, the resistance and inductance in this path should be minimi zed. pwm v ds v dd c byp fan3100 figure 44. current p ath for mosfet t urn - o ff truth table of logic operation the truth table indicates the operational states using the dual - input configuration. in a non - inverting driver configuration , the in - pin should be a logic lo w signal. if the in - pin is connected to logic high , a disable function is realized, and the driver output remains low regardless of the state of the in+ pin. in+ in - out 0 0 0 0 1 0 1 0 1 1 1 0 in the non - inverting driver configuration in figure 45 , the in - pin is tied to ground and the input signal (pwm) is applied to in+ pin. the in - pin can be connected to logic high to disable the driver and the output remains low , regardless of the state of the in+ pin. vdd gnd in - in + out pwm fan 3100 figure 45. du al - i nput d river enabled, n on - i nverting c onfiguration in the inverting driver application show n in figure 46 , the in+ pin is tied high . pulling the in+ pin to gnd force s the output low , regar dless of the state of the in - pin. vdd gnd in - in + out pwm fan 3100 figure 46. du al - i nput d river e nabled , i nverting c onfiguration
www.onsemi.com 16 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver operational waveforms at pow er up, the driver output remains low until the v dd voltage reaches the turn - on threshold. the magnitude of the out pulses rises w ith v dd until steady - state v dd is reached. the non - inverting operation illustrated in figure 47 show s that the output remains low until the uvlo threshold is reached, then the output is in - p hase w ith the inpu t. v dd in+ in- out turn-on threshold figure 47. no n - i nverting s tart - u p w aveform s for the inverting configuration of figure 46 , start - up w aveforms are show n in figure 48 . with in+ tied to v dd and the input signal a pplied to in ? , the out pulses are inverted w ith respect to the input. at pow er up, the inverted output remains low until the v dd voltage reaches the turn - on threshold, then it follow s the input w ith inverted phase. v dd in+ (v dd ) in- out turn-on threshold figure 48. i nverting s t art - u p w aveform s thermal guidelines gate drivers used to sw itch mosfets and igbts at high frequencies can dissipate significant amounts of pow er. it is important to determine the driver pow er dissipation and the resulting junction temperature in the applic ation to ensur e that the part is operating w ithin acceptable temperature limits . the total pow er dissipation in a gate driver is the sum of tw o components ; p ga t e and p dynamic : p total = p ga t e + p dynamic ( 1 ) gate d rivi ng l oss : the most significant pow er loss results from supplyin g gate current (charge per unit time) to sw itch the load mosfet on and off at the sw itching frequency. the pow er dissipation that results from driving a mosfet at a specified gate - source voltage , v gs , w ith gate charge , q g , at sw itching frequency , f sw , is determined by : p ga t e = q g ? v gs ? f sw ( 2 ) dynamic pr e - drive / s hoot - through c urrent: a pow er loss resulting from internal current consumption under dynamic operating conditions , including pin pull- up / pull - dow n resistors , can be obtained using the i dd (no - load) vs. frequency graphs in typical performance characteristics to determine the current i dynamic draw n from v dd under actual operating conditions : p dynamic = i dyn a mi c ? v dd ( 3 ) once the pow er dissipated in the driver is determined, the driver junction rise w ith respect to circuit board can be evaluated using the follow ing thermal equation, assuming
www.onsemi.com 17 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver typical application diagrams in+ in- out vdd v in pgnd fan3100 pwm enable active low 1 2 3 4 5 6 agnd figure 49. forward converter, primary - side gate drive (mlp package show n) v in q2 v sec d1 d2 q1 t1 v dd cc pwm 0.1f t2 fan3100 figure 50. driver for two - t ransistor forw ard converter gate transformer v in v out pwm control/ isolation q5 l q2 v sec d1 d2 q1 q3 t1 isolation v drv fan3100 sr figure 51. secondary synchron ous rectifier driver v dd fan3100c in out r c delay in out figure 52. programmable delay using cmos input
w ww.onsemi.com 18 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver t able 1. related products part number type gate dr ive ( 11) (sink /src) input threshold logic package fan3100c single 2 a +2.5 a / - 1.8a cmos single channel of tw o - input/one - output s o t2 3 - 5, mlp6 fan3100t single 2 a +2.5 a / - 1.8a ttl single channel of tw o - input/one - output s o t2 3 - 5, mlp6 fan3226c dual 2 a +2.4 a / - 1.6 a cmos dual inverting channels + dual enable soic8, mlp8 fan3226t dual 2 a +2.4 a / - 1.6 a ttl dual inverting channels + dual enable soic8, mlp8 fan3227c dual 2 a +2.4 a / - 1.6 a cmos dual non - inverting channels + dual enable soic8, mlp8 fan3227t dual 2 a +2.4 a / - 1.6 a ttl dual non - inverting channels + dual enable soic8, mlp8 fan3228 c dual 2 a +2.4 a / - 1.6 a cmos dual channels of two - input/one - output, pin config.1 soic8, mlp8 fan3228t dual 2 a +2.4 a / - 1.6 a ttl dual channels of two - input/one - output, pin config.1 soic8, mlp8 fan3229c dual 2 a +2.4 a / - 1.6 a cmos dual channels of t wo - input/one - output, pin config.2 soic8, mlp8 fan3229t dual 2 a +2.4 a / - 1.6 a ttl dual channels of two - input/one - output, pin config.2 soic8, mlp8 fan3223c dual 4 a +4.3 a / - 2.8 a cmos dual inverting channels + dual enable soic8, mlp8 fan3223t dual 4 a +4.3 a / - 2.8 a ttl dual inverting channels + dual enable soic8, mlp8 fan3224c dual 4 a +4.3 a / - 2.8 a cmos dual non - inverting channels + dual enable soic8, mlp8 fan3224t dual 4 a +4.3 a / - 2.8 a ttl dual non - inverting channels + dual enable soic8, m lp8 fan3225c dual 4 a +4.3 a / - 2.8 a cmos dual channels of two - input/one - output soic8, mlp8 fan3225t dual 4 a +4.3 a / - 2.8 a ttl dual channels of two - input/one - output soic8, mlp8 no t e : 11. typical currents w ith out at 6 v and v dd = 12 v.
w ww.onsemi.com 19 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver physical dimens ions top view 0.05 c 0.05 c 2x 2x 2.0 2.0 pin#1 ident a b side view recommended land pattern bottom view seating plane 1 3 4 6 4 6 3 1 pin #1 ident 0.65 1.30 1.21 0.52(6x) 0.90 0.42(6x) 0.65 2.25 1.68 (0.40) (0.70) notes: a. pac kage does not fully conform t o jedec mo-229 registration b. d imensions are in millimeters. c. d imensions and tolerances per asm e y14.5m, 2009. d. l and pattern recommendation is exist ing industry land pattern. e. d rawing filename: mkt-mlp06krev5. 2.000.05 1.400.05 0.800.05 (0.20)4x 0.320.05 0.10 c a b 0.05 c 0.300.05 (6x) (6x) (0.60) 0.08 c 0.10 c 0.750.05 0.0250.025 c 0.200.05 1.72 0.15 f igure 53. 2x2 mm , 6- lead , m olded lead less package (m lp ) p ackage drawings are provided as a service to customers considering on semiconductor components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a n on semiconductor representative to verify or obtain the most recent revision. package specifications do not expand the terms of on semiconductor ?s worldwide terms and conditions, specifically the warranty therein, which covers on semiconductor products.
w ww.onsemi.com 20 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver physical dimensions 5 1 4 3 2 land pattern recommendation b a l c 0.10 c 0.20 c a b 0.60 ref 0.55 0.35 seating plane 0.25 gage plane 8 0 notes: unless othewise specified a) t his package conforms to jedec m o-178, issue b, variation aa, b) al l dimensions are in millimeters. 1.45 max 1.30 0.90 0.15 0.05 1.90 0.95 0.50 0.30 3.00 2.60 1.70 1.50 3.00 2.80 symm c 0.95 0.95 2.60 0.70 1.00 see detail a 0.22 0.08 c) ma05brev5 top view (0.30) f igure 54. 5- lead sot - 23 package drawings are provided as a service to customers considering on semiconductor components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and con tact a n on semiconductor representative to verify or obtain the most recent revision. package specifications do not expand the terms of on semiconductor ?s worldwide terms and conditions, specifically the warranty therein, which covers on semiconductor prod ucts.
w ww.onsemi.com 21 fan3100 c / fan3100t ? single 2 a high - speed, low - side gate driver on semiconductor and the on semiconductor log o are trademarks of semiconductor components industries, llc dba on semiconducto r or its subsidiaries in the united states and/or other countries. on semiconductor owns the rig hts t o a number of patents, trademarks, copyrig hts, trade secrets, and other intellectual property. a listing of on semiconductor?s product/patent coverag e may be accessed at www.onsemi.com/site/pdf/patent - marking .pdf. on semiconductor reserves the rig ht to mak e chang es without further notice to any products herein. on semiconductor makes no warranty, representation or g uarantee reg arding the suitability of its products for any particular purpose, nor does on semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, conseq uential or incidental damag es. buyer is responsible for its products and applications using on semiconductor produc ts, including compliance with all laws, reg ulations and safety req uirements or standards, reg ardless of any support or applic ations information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer app lication by customer?s technical experts. on semiconductor does not c onvey any license under its patent rig hts nor the rig hts of others. on semiconductor products are not desig ned, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreig n jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semiconductor products for any su ch unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless ag ainst all claims, costs, damag es, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleg es that on semiconductor was neg lig ent reg arding the desig n or manufacture of the p art. on semiconductor is an eq ual opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 - 675- 2175 or 8 00- 344- 3860 toll free usa/canada fax : 303 - 675- 2176 or 800 - 344- 3867 toll free usa/canada email : orderlit@onsemi.com n . american technical support : 800 - 282- 9855 toll free usa/canada. europe, middle east and africa technical support : phone: 421 33 790 29 10 japan customer foc us center phone: 81 -3- 5817- 1050 on semiconductor website : www.onsemi.c om o rder literature : http://www.onsemi.com/orderlit f or additional information, please contact your local sales representative

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